Agilent Technologies 8133A Instrukcja Obsługi Pobierz pdf (Strona 33)

Testing Performance 3

16800 Series Portable Logic Analyzers Service Guide 33

To Test the Minimum Master to Master Clock Time and Minimum Eye Width

The specifications for the logic analyzer define a minimum

master to master clock time and a minimum data eye width

at which data can be acquired. This test verifies that the

logic analyzer meets these specifications.

Eye finder is used to adjust the sampling position on every

tested channel. Eye finder must be used to achieve minimum

data eye width performance.

First, the logic analyzer will be tested in the 250 Mb/s state

mode. Then it will be tested in the 500 Mb/s state mode.

In the 250 Mb/s state mode each pod will be tested with its

respective clock.

The 500 Mb/s mode has only one clock (Clk1). All tests in

the 500 Mb/s mode will use clock Clk1.

A sample of four channels on each pod will be tested, one

pod at a time, in both 250 Mb/s state mode and 500 Mb/s

state mode.

The logic analyzer will be configured to acquire data on both

edges of the clock, so the test frequency is set to half of the

acquisition speed.

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Agilent Technologies 8133A Instrukcja Obsługi Strona 33