
Operation
48
Serial BERT 12.5 Gb/s User Guide
4.4 Power-On State
The power-on state of the N4962A is set after turning the rear Power switch
on. The internal clock is active and generates a 10.0 GHz clock. The PRBS
generator is off. The error detector is off, in training mode, and will not
accumulate errors. The error detector light may indicate errors if the default
sampling position is incompatible with the cable length, or if the OUT/OUT¯¯¯
port(s) are not connected to the IN/IN¯¯port(s).
Table 16. N4962A power-on state
Local push-button (vs GPIB) control
On
¯¯¯¯
Error detector clock phase adjustment
31
-1
-injection mode
PRBS errors added per second
Error detector data sense
Komentarze do niniejszej Instrukcji