Agilent Technologies N4962A Podręcznik Użytkownika Pobierz pdf (Strona 25)

System Details and Performance Specifications

Serial BERT 12.5 Gb/s User Guide 25

Figure 5. N4962A block diagram – internal clock system

The internal LF 1/16th-rate clock can be phase locked to an external source in

order to synchronize the N4962A with the external device. To synchronize the

clocks, follow the procedure detailed below. The internal or external LF clock is

available from the buffered LF TrigO connector.

To ensure phase lock of an external LF clock applied to the ExtCKI port, the

following procedure must be used:

1. Turn off the external signal generator RF output

2. Set external signal generator to new 1/16th-rate RF frequency

3. Set N4962A to new HF frequency value (or nearest value)

4. Turn on the external signal generator RF output

5. Turn off the N4962A internal synthesizer (change "synth" to 0)

Users wanting to change frequency from this condition should:

1. Turn on the internal synthesizer (synth to 1)

2. Turn off the external signal generator RF output

3. Set the external signal generator to the new 1/16th-rate frequency

4. Set the N4962A to new HF frequency value (or nearest value)

5. Turn on the external signal generator RF output

6. Turn off the N4962A internal synthesizer (synth to 0)

The clocks should now be phase locked to the new frequency.

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Agilent Technologies N4962A Podręcznik Użytkownika Strona 25