Agilent Technologies 54502A Instrukcja Obsługi Strona 41

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4. In the State Format Specification assign Clock Period > 60 ns. Also assign
lower 8 channels of the pod under test to a label as shown in next figure . If
testing H P 1650B then assign falling edge of L clock for all pods. If testing
HP 1651B then assign falling edge of J clock for all pods. Refer to steps a
through c if unfamiliar with the menus.
a. Press front-panel FORMAT key.
b. Move cursor to Clock field of menu. Use cursor and SELECT key to
set appropriate clock for falling edge as in next figure.
Figure 3-5. State Format Specification for Data Test 1
Figure 3-6. Clock Assignment for Data Test 1
Performance Tests HP 1650B/1651B
3-6 Service Manual
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