Agilent Technologies N4962A Podręcznik Użytkownika Pobierz pdf (Strona 4)

BER Tester with an External 1/16

Rate Clock for 10 Gb/s

Applications

The N4962A serial BERT 12.5 Gb/s can also be synchronized to an external

1/16th rate clock for BER measurements from 9.85 to 11.35 Gb/s. This applica-

tion is ideally suited for synchronizing the BERT with the system clock of a DUT,

like a transceiver, SERDES, or CDR.

A block diagram is shown in Figure 5. The external low-frequency (LF, clock/16)

signal is connected to ExtCKI. The BERT synth option should be changed to 0,

and the freq option to the approximate frequency rate (clk/16 * 16).

1, 2

1. The clock signal applied to the ExtCKI port must be within the range of 615 to 709 MHz; this

signal is multiplied by 16 and output from the TX CKO and RX CKO outputs. Frequencies outside

this range will not be correctly multiplied by the BERT internal clock system.

2. To ensure the phase lock of an external LF clock applied to the ExtCKI port, reference the

procedure detailed in Section 2.2 of the User Guide.

LF TrigO

HF TrigO

JitterI

EXT CKI

TX CKO

~IN

~OUT

OUT

RX CKI

RX CKO

TX CKI

N4962A serial BERT

12.5 Gb/s

DUT clk/16

Figure 5. Block diagram – BER measurement of DUT synchronized with 1/16th rate clock

1 2 3 4 5 6 7 8 9 10 11 12

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Agilent Technologies N4962A Podręcznik Użytkownika Strona 4