Agilent Technologies DisplayPort Instrukcja Użytkownika

Display Port Physical Layer Testing Challenges) Agilent Technologies Testing Overview Jim Choate

DisplayPort Source Testing 1.  3-1: Eye Diagram 2.  3-2: Level (Non PE) 3.  3-3: Pre-Emphasis Level 4.  3-4: Inter Pair Skew 5.  3-11: Non ISI Jitter

U7232B DP TX test sw speeds up testing (1) Select the DP Test Setup Configure Project settings such as the Device type and test type

Automated SW Speeds Up Testing (2) Selecting the tests. Select the DP DUT supported capabilities to test Selecting the Physical connections.

DP TX Test Demo " Demo with Mike Engbretson of Granite River Labs

1.  8-1: AUX Eye Test 2.  8-2: AUX Sensitivity 3.  8-3: AUX- Termination 4.  8-4: AUX+ Termination 5.  8-5: Inrush Current More tests coming for Fas

Testing DisplayPort Transmitters Patterns Used: #  RBR/HBR: PRBS7 and D10.2 #  HBR2: HBR2 CPAT: long pattern of coded 0’s D10.2: (ha

Testing !"#$%&'(%)$"*%+,$%-.$"%/.0"12%-"3',1"4%&5,26%%/7%/89%&&8%:.2"%7;"!<,.61.*

Source Test Setup (one lane) With Probe Amp and N5380A probe head Direct A-B connection: no probe Amp or probe head

New for DP1.2: HBR2 EQ + - Connector TP1 Channel EQ + - TP3 TP3Eq Txp Txn Rxn Rxp Tx Rx Fixture Eye after Channel Eye after Equalizer TP3Eq=TP2 Acquis

Display Port transmitter test challenges •  Transmitter test cases can be significant •  In the most complex case there are 100s of test cases •  Full

Presentation Topics Display Technologies Overview Testing DisplayPort (TX focus) DisplayPort Compliance Testing and Program Agilent DisplayPort soluti

Common Failures/Issues •  Transmission path at 5.4Gbps •  Hosts have the biggest challenge due to path length •  At 5.4Gbps losses due to FR4 can hurt

Agilent DisplayPort 1.2 Test Solutions Source Test Solution DSO90000A Infiniium Real Time Oscilloscopes U7232B DisplayPort Compliance Test SW Comput

Another Measurement Issue: Realtime De-Embedding In performing a one block de-embed, the transmitter’s output impedance is assumed to be 50 ohms. Th

This is the waveform we get so we store it into memory 1… It represents an insertion loss removal---a one block de-embed

Now we add the S22 file (.s1p) which is purely a load function… Note: it is not necessary to put the s1p for the simulation circuit because the receiv

This is the waveform we get so we store it into memory 2…

The current trace in yellow overlaps the trace that comprehends the S22… Since the extended scope input is a good 50 ohms, there is little interactio

Backup

One-box Solution for Cable/Connector Compliance Test S Parameters Cable & Connector Z TDR Intra-Pair Skew Inter-pair Skew Far End Noise Return

Generalized Testing of High Speed Links TP1: Interface Output of Transmitter TP1-TP2: Cable Measurements TP3: Tx through Cable TP4: Tx through Cable a

Overview: DisplayPort Technology Standard DisplayPort eDP iDP MYDP MYDP Type Lanes Bit Rate Version Status Box-to-Box 1, 2, or 4 1.62, 2.7, 5.4 V1.2

DP AUX Channel Validation $ New for compliance testing for DP 1.2 $ Key operation for automation $ Key functionality for interoperability and interop

DP Technology: Main Link Lanes Silicon structures: •  Structure leveraged from PCI Express •  Implementable on sub 65nm process •  Termination Voltage

DisplayPort Technology: Interface Overview DPCD / EDID !  1 to 4 unidirectional high speed lanes –  Fixed data rate independent of display raster (ref

DisplayPort Technology: Interface Overview DPCD / EDID !  3 Different Data Rates: 1.62, 2.7, 5.4 Gbs !  4 Tx Level Settings: 400, 600, 800, 1200 mV (n

DP Technology: AUX Channel, DPCD •  Designated Control Link lane called ‘the AUX Channel’ specified. Operates at 1Mbs and is used in Link Training a

DisplayPort DisplayPort monitor "  TBT switches to full DisplayPort mode "  All four lanes used to transport video "  DisplayPort com

DisplayPort vs HDMI… a Comparison HDMI DisplayPort Market Configuration Technology Ownership Compliance Std/Royalty Bit Rate HDTV/Gaming PCs TMDS (8B/